FEATURES:
- Support for clear channel T3, Channelized T3 to T1, n x T1, full-rate T1, Channelized T1, fractional T1, or DS-0 connections
- Integrated DSUs
- Support for all major encapsulations, including MLPPP and multilink Frame Relay (MLFR)
- Support for link fragmentation and interleaving (LFI) over Frame Relay (FRF.12) and MLPPP
Highly modular, flexible, intelligent interface processors:
- Superior flexibility, supporting a combination of interface types on the same interface processor for consistent services, independent of access technology
- Pioneering programmable interface processors that provide flexibility for the service diversity required in next-generation networks
- Innovative design that supports intelligent service delivery without compromising on performance
Increased speed-to-service revenue:
- The scalable, programmable Cisco architecture extended to 10 Gbps dramatically improves customer density, increasing potential revenue per platform.
- Interface breadth (copper, channelized, Packet over SONET/SDH [PoS], ATM, and Ethernet) on a modular interface processor allows service providers to roll out new services more quickly, helping ensure that all customers receive consistent, secure, and guaranteed services.
- High-density Small Form-Factor Pluggable (SFP) interfaces are featured for high-port-count applications with reach flexibility. Future optical technology improvements can be adopted using existing SPAs.
Dramatically improved return on your routing investment:
- Improved slot economics and increased density reduce capital expenditures (CapEx).
- The ability to easily add new interfaces as they are needed enables a "pay-as-you-grow" business model.
- SPAs are shared across multiple platforms, and can be easily moved from one to another, providing consistent feature support, accelerated product delivery, and a significant reduction in operating expenses (OpEx) through common sparing as service needs change.
FUNCTIONS:
- Up to 1024 n x DS-0 channels (where n is 1 to 24) with no T3 configured
- Up to 400 n x DS-0 channels (where n is 1 to 24) with one or more T3 configured
- Support for full-rate (clear channel) T3, Channelized T3 to T1
- Integrated DSUs
- Internal or line-derived (loop) clocking selectable
Loopback capabilities:
- Local and remote loopback
- Response to embedded loopback commands
- Insertion of loopback commands into transmitted signal
- Bit-error-rate-testing (BERT) pattern generation and detection per channel
- Programmable pseudorandom pattern up to 32 bits long
- All 0s, all 1s, 215, 220, 220 Quasi-Random Signal Sequence (QRSS), 223, alternating 0s and 1s, 1-in-8, and 3-in-24
- 32-bit error-count and bit-count registers
- Fully independent transmit and receive sections
- Detection of test patterns with bit error rates up to 10-2
- 24-hour history maintained for error statistics and failure counts, at 15-minute intervals
- 16- and 32-bit cyclic redundancy check (CRC); 16-bit default
- Full-duplex connectivity at T3 rate (44.736 MHz)
- C-Bit or M23 framing
- Subrate and scrambling support of Quick Eagle Networks (formerly Digital Link), Larscom, ADC Kentrox, Adtran, and Verilink DSUs
- Binary 3-zero substitution (B3ZS) line coding
- Maintenance data link (MDL)
- T3 far-end alarm and control (FEAC) channel support
- Line build-out up to 450 ft (135m)
Alarm monitoring:
- AIS
- OOF
-Loss of signal (LOS)
- Far-end receive failure (FERF)
Performance data collection:
- Line coding violation (LCV)
- Framing bit errors (FERR) (F- or M-bit errors)
- P-bit error counts (path-parity errors)
- C-bit error counts
- Far-end block error (FEBE) counts
Physical interface:
- 1.0 and 2.3 RF connectors (75-ohm impedance)
- 1.0 and 2.3 RF-to-BNC adapter cable option
ENVIRONMENTAL PROPERTIES:
Operating Temperature: 41 to 104 F (5 to 40 C)
Storage Temperature: -38 to 150 F (-40 to 70 C)
Op